A memory device or memory can generally be described as hardware that can store data for later retrieval. Some memory devices include a set of transistors used to store data (represented, for example, by an electrical charge) and a set of transistors used to control access to the data store. Sizes of transistors have shrunk to 45 nm and will soon reach 32 nm. As sizes have decreased, the margin of errors acceptable during manufacturing have decreased. As a result, the manufactured transistors exhibit larger variability during operation.
The large increase in variability of transistor technologies has negatively affected memory devices and their read stability. Read stability is the ability of the memory device to retain the correct data when accessed in the presence of noise. Commonly, read stability is measured using static noise margin (SNM). Large variations in manufactured transistors cause a reduction in the memory device's static noise margin. This reduction in static noise margin lowers the bit cell robustness and tolerance against noise, and hence, lowers memory yield due to increased failures.
Slightly reducing a memory device's bit line voltage compared to the supply voltage significantly improves the memory device's static noise margin. However, in memory designs the bit line is generally precharged to a supply voltage before accessing the memory. There have been several attempts to reduce the bit line voltage to improve read stability. Previous attempts have shown large sensitivity to process, temperature and voltage variations during manufacturing that may limit their effectiveness to improve read stability. Some of these attempts include the pulsed bit line scheme, dual supply voltages, and dynamic cell biasing.
In a pulsed bit line scheme, a pull down device is connected to the bit line. After precharging the bit line to the supply voltage, a narrow pulse is applied on the pull down device that lowers the bit line voltage and improves read stability. This technique is very sensitive to the generation of this narrow pulse, especially because the pulse width will vary with process, voltage, and temperature variations during manufacturing of the transistors and environmental variations.
Another attempt uses two supply voltages, one for the bit cell, and another for the bit line, where the bit line voltage is lower than the bit cell voltage. Adding additional supply voltages is a difficult task and complicates the physical design and verification of the chip.
Yet another attempt to reduce bit line voltage includes using an NMOS device to precharge the bit line to reduce the bit line voltage by the threshold voltage of the NMOS device. A low threshold voltage NMOS device is used in this case, which increases process complexity and cost, e.g., requiring additional masks. In addition, the threshold voltage has strong dependence on process, voltage, and temperature variations.
These three attempts to improve memory read stability are sensitive to manufacturing variations and as such are difficult to implement and are costly to implement. Such cost is further increased when multiple supply voltages or an NMOS device is implemented in the precharge circuitry. Thus, there is a need for an improved read stability in memory designs that decrease sensitivity to manufacturing variations without incurring additional cost.